1. Field of the Invention
This invention is related to a memory controller which controls the flow of data going to and from a main memory. This invention is related also to a bus system and an integrated circuit, which include the memory controller, and a control method of the integrated circuit.
2. Description of Related Art
A system scale in large scale integration (LSI) becomes larger, and a larger number of bus masters access a main memory through a bus path. There are some methods of connecting multiple bus masters to the main memory. One method is connecting multiple bus masters hierarchically. Another method is providing a larger number of input/output ports to the main memory and connecting the bus master with each input/output port of the main memory.
The memory controller gives the bus masters an access right to the memory and arbitrates memory access requests of the bus masters. This arbitration operation is performed so that the processing efficiency of data transfer from the bus master to the memory is maximized according to specifications and characteristics of the memory. In other words, the arbitration is operated so that the throughput is maximized. For example, the memory controller of Multibank Dynamic Random Access Memory (Multibank DRAM) manages the memory access requests REQ as a queue. The memory controller arbitrates the memory access requests so that memory operation switches between writing and reading operation with a minimum number of switching times. The arbitration is also performed so as to prevent memory bank conflicts. In this way, the arbitration of the memory controller enhances the processing efficiency of data transfer between the bus master and the memory.
When the LSI is mounted in an electrical device utilizing sound data, video data or the like, the transfer speed of the data processed by the LSI directly influences the usability for the users. In the memory controller of the LSI, when sound data and video data are transferred between the bus master and the memory, the delay time needs to be set within a predetermined time. The delay time means the waiting time for the bus master, which is from the time the bus master sends an access request REQ until the time the bus master actually transfers the data. Japanese Unexamined Patent Application Publication No. 9-259080 and “Prime Cell Dynamic Memory Controller (PL340) r0p0 Technical Reference Manual Ref: DD10331C”, <URL: http://www.arm.com/products/solutions/PrimeCellMemCtrl.html> disclose the control method of the memory controller, in which a maximum delay time of data transfer is predetermined and the data is transferred within the maximum delay time.
Japanese Unexamined Patent Application Publication No. 9-259080 discloses that the maximum delay time is determined depending on the change in frequency of a bus between the sending side and the receiving side in order to set the optimum value of the maximum delay time. “Prime Cell Dynamic Memory Controller (PL340) r0p0 Technical Reference Manual Ref: DD10331C” discloses that the memory controller receives read access requests from the bus masters, expects a predicted maximum delay time of the bus, and determines the maximum delay time in consideration of the predicted maximum bus delay time. In the control method of the memory controller, when a read access cannot be executed within the maximum delay time, this read access is preferentially processed.
However, in the memory controller according to Japanese Unexamined Patent Application Publication No. 9-259080, when the plurality of bus masters request access memory, accesses are concentrated in the bus and a waiting time, which is from the time the bus master sends access request until the time the connection between the bus master and the memory controller is built is changed according to the busy condition of the bus. In the memory controller, the maximum delay time of data transfer is determined only based on a bus frequency and the busy condition is not considered at determining the maximum delay time. In the memory controller according to Japanese Unexamined Patent Application Publication No. 9-259080, there is a problem that the maximum delay time cannot be optimally determined for actual system condition.
In the control method of the memory controller according to “Prime Cell Dynamic Memory Controller (PL340) r0p0 Technical Reference Manual Ref: DD10331C”, the maximum delay time for memory access is determined based on the maximum bus delay time. As a result, in the control method of the memory controller according to “Prime Cell Dynamic Memory Controller (PL340) r0p0 Technical Reference Manual Ref: DD10331C”, the maximum delay time is set shorter than necessary. When the maximum delay time is set short, time out signals informing exceedance of the maximum delay time are frequently input to the arbiter. Commonly, the arbiter arbitrates the memory accesses so that the processing efficiency of data transfer from the bus master to the memory is maximal. However, when the time out signals are often input to the arbiter, arbitration for maximum processing efficiency is frequently interrupted. In the control method of the memory controller according to “Prime Cell Dynamic Memory Controller (PL340) r0p0 Technical Reference Manual Ref: DD10331C”, there is a problem that processing efficiency of data transfer decreases caused by the time out signals inputted.